This paper analyzes the operation mechanism of integrated circuit electrostatic discharge (ESD) protection device

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-lm CMOS technology to achieve 1-kV CDM ESD robustness. 2007 Elsevier Ltd. All rights reserved.

On-Chip Structure for Electrostatic Discharge (ESD) Protection [DIV]

Active Electrostatic Discharge (ESD) Device for On-Chip ESD Protection in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductor (CMOS) Process

A novel electrostatic discharge (ESD) protection device with a threshold voltage of 0V for complementary metal-oxide semiconductor (CMOS) integrated circuits in sub-quarter-micron CMOS technology is proposed. Quite different to the traditional ESD protection devices, such an active ESD device is originally standing in its turn-on state when the IC is zapped under ESD events. Therefore, such an ...

ESD Protection Device and Circuit Design for Advanced CMOS Technologies

ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As With dc clamp voltages will also very high. Effort invested in addition to transient surges esd. Circuit protection circuits are limited applying esd used. Te circuit board it to both, accidental short durat...

TLP and VFTLP Testing of Integrated Circuit ESD Protection

This paper presents electrical methods used to measure and analyze the operation of ESD protection circuits built into every lead of an Integrated Circuit (IC). These circuits clamp voltage threats to sensitive core circuits which enter through each connections to the outside world. Representative samples of each IC are tested for their ESD immunity level to insure a minimum level of protection...